Memora8 System Bus and SB/SBI Instructions
Document version: 1.0 Status: Specification
Purpose
The System Bus is Memora8’s privileged control interface for processor and device operations. It is separate from ordinary program memory: LW and SW access addresses through the CPU’s memory and MMU path, while SB and SBI access the System Bus contract directly. The System Bus is intended for control and status exchange, device commands, and platform services rather than general-purpose data storage.
This document describes the instruction-level interface and the canonical 32-word System Bus contract. Device operations define the meaning of their selectors, commands, arguments, results, and status values.
System Bus word contract
The canonical interface has 32 words, each 32 bits wide. Word addresses are numbered 0 through 31 and are not byte addresses.
| Word | Role |
|---|---|
| 0–30 | DATA[0..30]: arguments, data, and response values defined by the selected device operation |
| 31 | Packed command descriptor and commit word; writing it launches the operation using the prepared data words |
Word 31 contains the packed descriptor cmd:grp:dev, with field widths 22:5:5:
| Bits | Width | Field |
|---|---|---|
[31:10] |
22 | cmd — command code |
[9:5] |
5 | grp — device group |
[4:0] |
5 | dev — device within the group |
Software places arguments and data in words 0–30, then writes the packed descriptor to word 31. That write is the operation’s commit point: the selected group and device receive a snapshot of the prepared data words. The meaning of each command, argument, result, and status value belongs to the relevant device specification; the shared layout does not assign a universal meaning to every data word.
The System Bus is a distinct architectural interface, not ordinary program memory. LW and SW do not access it.
SB and SBI
SB and SBI are privileged instructions. Both encode a 17-bit control value with the same interpretation:
- bit 16 selects the operation:
0means write,1means read; - bits
[15:0]contain the word address, which must be in the range 0–31.
For SB, the control value is taken from rs2. For SBI, it is the sign-extended 17-bit immediate as encoded by the ISA; its low 17 encoded bits carry the control value. In either form, rs1 supplies the 32-bit write value. For a read, the selected word is returned in rd; writes do not produce a register result. Writes to r0 have no effect, consistent with the ISA’s constant-zero register.
Conceptual forms:
SB rd, rs1, rs2 ; control = rs2
SBI rd, rs1, control ; control = immediate
The assembler’s accepted spelling and operand syntax are toolchain-specific; these forms describe the decoded fields, not a guarantee about every assembler’s textual grammar.
Examples
The sequence below is pseudocode for privileged software; it illustrates the required write order without prescribing assembler syntax.
write SystemBus[0], argument_0
write SystemBus[1], argument_1
write SystemBus[31], (cmd << 10) | (grp << 5) | dev
Each pseudocode write is performed by an SB or SBI instruction with bit 16 clear and the target word address in bits [15:0]. A read uses bit 16 set and the desired word address in bits [15:0]; the returned word is written to rd.
Privilege, faults, and ordering
User-mode code cannot execute SB or SBI; attempting to do so raises a privilege fault. Access to a word outside 0–31 is invalid and raises an implementation-defined System Bus fault. The simulator executes a successful access at instruction commit, after capturing the source operands so later pipeline activity cannot change the transaction’s values.
The interface has no ISA-level retry instruction or wait/result handshake encoded in SB/SBI. A device contract defines how software observes completion and errors, typically through response/status words or a subsequent device query. Software should follow that device contract and must not assume that a command’s result is available immediately unless the contract guarantees it.
Platform implementation notes
The canonical command sequence stages arguments in words 0–30, then writes the cmd:grp:dev descriptor to word 31. This final write commits one command snapshot to the selected device. The device contract defines valid operations, response placement, status codes, and any required polling or synchronization. Commands and device identifiers outside that contract have no defined behavior.
Relationship to the ISA
The opcode assignments and instruction fields are defined in the Memora8 Instruction Set Architecture. This document specifies the System Bus contract; it does not redefine ordinary loads/stores or assign device-specific command codes.
Versioning
The document version is independent of hardware and software release versions. Changes to the 32-word contract, descriptor field layout, control-bit meaning, privilege rules, or commit behavior require review against the ISA model and its implementations.